TSMC's Second Japan Fab Was Upgraded to 3nm for the AI Boom — Then an Earthquake Paused Construction

Taiwan's government approved TSMC's plan to deploy advanced 3-nanometer production technology at its second fab under construction in Kumamoto, Japan. The facility was originally planned to manufacture older 6-to-12nm chips; upgrading it to TSMC's advanced 3nm node is a direct response to soaring global demand for AI-related chips, which has outpaced what TSMC's existing advanced-node capacity in Taiwan and the US can absorb.

The upgraded fab is scheduled to begin installing equipment and come online in 2028, with planned monthly capacity of 15,000 12-inch wafers. Committing an entire second Japan facility to the most advanced process node TSMC currently ships in volume signals the company sees AI-chip demand as durable enough to justify re-purposing already-underway construction.

The timing carries a real near-term complication: in early August 2026, construction was briefly suspended as a precaution against aftershocks following regional earthquake activity, then resumed after additional safety inspections. TSMC has not issued a revised timeline despite the suspension, meaning the 2028 target officially stands. For a facility being upgraded specifically to meet urgent AI-chip demand, any construction disruption is worth tracking closely — a fab built to relieve a capacity crunch that then falls behind schedule doesn't relieve anything on the original timeline.